FPGA Programmable Logic Block Evaluation using Quantified Boolean Satisfiability

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated in this paper is FPGA PLB evaluation where the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way. Manuscript received October 20, 2005; revised December 4, 2005. A. Ling is with the University of Toronto. D. Singh is with Altera Corporation. S. Brown is with Altera Corporation and the University of Toronto.